Method and apparatus for securing electronic circuits

ABSTRACT

A method and apparatus for protecting the stored information on an integrated circuit from being compromised through reverse engineering. To do so, the method and apparatus splits the functionality of an integrated circuit into two separate integrated circuits, which are then connected in an interlocking manner. A detection circuit monitors the interconnection of the two separate integrated circuits. Upon detection of a break in the interconnection of the two circuits, the detection circuit destroys the data stored in the two separate integrated circuits. The two integrated circuits are connected in a flip-chip fashion, thereby preventing access to the underlying conduction paths and charge storage sites which are normally used in reverse engineering an integrated circuit.

BACKGROUND OF THE INVENTION

[0001] The present invention relates generally to methods andapparatuses for protecting electronic systems from theft of sensitiveinformation, and more particularly to a method and apparatus forprotecting an electronic system from theft of sensitive information bypreventing reverse engineering of the circuits employed in theelectronic system.

[0002] Many electronic systems and devices use data encryption securityschemes to protect sensitive information, e.g., personal data, financialtransaction authorization codes, security passwords, etc. These schemesrely on a stored encryption key or security key that must be physicallyand electrically inaccessible to unauthorized access.

[0003] Storage methods include magnetic storage, e.g., disk drives,optical storage, compact disks and electronic media (such as memoryintegrated circuits). Disk storage, both magnetic and optical, is notsecure because data can be read off the disks and reverse engineered byvarious methods to determine the encryption or security keys.

[0004] For added security, the keys can be stored in an electronicmemory circuit on an integrated circuit. Specialized equipment isrequired to remove the packaging materials of these devices and reverseengineer the key. However, integrated circuits are vulnerable to reverseengineering —even data stored in FLASH or EEPROM or other non-volatilememory or battery backed memories.

[0005] Some methods used to enhance the security of these integratedcircuits include physical approaches, e.g., 1) locking or sealing casesto enclose the circuit boards on which memory devices are mounted, 2)using special packaging that destroys the integrated circuit if there istampering, or 3) using metal layers to mask the storage elements fromsensing equipment. For example, FIG. 3 depicts an implementation of thethird method above in a cross-sectional view. The chip including thetransistors is covered with several thick metallization layers. Asrecognized by the prior art, the transistor tubs generate heat that canbe scanned to determine which transistor is charged, thereby decodingthe stored information. Alternatively, circuit reverse engineering canbe performed to determine the encryption keys. To prevent either ofthese possibilities, thick layers of metallization are used to spreadthe thermal signature. This security protection can be defeated bypartial and complete removal of portions of the metallization layer.

[0006]FIG. 4 depicts a detailed view of the implementation shown in FIG.3. As evident, the thermal signature exists on the surface of the chip.Scanning equipment can also be used to detect the charge levels on thechip surface.

[0007] Other security methods include electronic circuitry, e.g.,circuits that detect removal of power to the system/device, sensors thatdetect tampering, and continuity circuits in the packaging or on theintegrated circuits that scramble stored data if tampering is detected.

[0008] All of the above methods are vulnerable to one sophisticated inthe art of reverse engineering. For example, continuity circuitry can bedefeated by ensuring that power is constantly applied, metal lids can beshorted with jumpers, ceramic packages that shatter if opened and metallayers deposited over portions of the integrated circuit can be etchedaway by physical and mechanical means.

[0009] Once the circuitry of the chip is exposed, sensing equipment,such as a low voltage scanning electron microscope (SEM) or a thermalscanner can be used to determine the stored charges of transistors onthe chip and decode the keys. Alternatively, probes can be used todirectly or indirectly sense charges on the chip.

[0010] The present invention is therefore directed to the problem ofdeveloping a method and apparatus for protecting an integrated circuitfrom being reverse engineered so that the stored information on thecircuit cannot be determined.

SUMMARY OF THE INVENTION

[0011] The present invention solves this problem by splitting thefunctionality of an integrated circuit into two separate chips, whichare then connected in an interlocking manner. In addition, the presentinvention provides a detection circuit that monitors the interconnectionof the two chips, and which destroys the stored data upon detection of abreak in the interconnection of the two chips.

[0012] In one embodiment of the present invention, the two chips areconnected in a flip-chip fashion, thereby preventing access to theunderlying conduction paths and charge storage sites which are used inreverse engineering an integrated circuit.

[0013] In an alternative embodiment of the above embodiment, theflip-chip is only provided over a portion of the active chip thatincludes the sensitive information. This reduces the size and complexityof the total device.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 depicts an exemplary embodiment of an apparatus accordingto one aspect of the present invention in a cross-sectional view.

[0015]FIG. 2 depicts a top view of the exemplary embodiment shown inFIG. 1.

[0016]FIG. 3 depicts a prior art implementation in a cross-sectionalview.

[0017]FIG. 4 depicts a detailed view of the prior art implementationshown in FIG. 3.

[0018]FIG. 5 depicts a cross-sectional view of an exemplary embodimentof one aspect of the present invention.

[0019]FIG. 6 depicts the exemplary embodiment shown in FIG. 5 in acircuit block diagram.

[0020]FIG. 7 depicts an exemplary embodiment in a flow chart form of acontinuity detection algorithm according to one aspect of the presentinvention.

[0021]FIG. 8 depicts an exemplary embodiment of an apparatus for use inan SRAM configuration according to one aspect of the present invention.

[0022]FIG. 9 depicts an exemplary embodiment of an apparatus accordingto one aspect of the present invention.

[0023]FIG. 10 depicts an exemplary embodiment of an apparatus accordingto one aspect of the present invention.

DETAILED DESCRIPTION

[0024] The present invention employs a chip-on-chip structure to providesecurity for the two chips involved. Attaching a second chip directly ontop of a first chip (i.e., the sensitive chip), which second chip iselectrically connected to the sensitive chip, protects the sensitivechip (or area of the sensitive chip) from external aggression or attack.This structure physically shields the integrated circuit at the pointwhere the sensitive data is stored, thereby preventing surface scanning.As a result of this configuration, the internal pins in this chipsandwich are also inaccessible to probes. Moreover, circuitry providedon the flip-chip or memory chip detects when the flip-chip is removed orwhen attempts are made to etch away portions of the flip-chip. Upondetection of such tampering, the sensitive data is then scrambled ordeleted. The sensitive data includes any information that one might wishto protect from theft, such as encryption keys, trade secret data,financial information, etc.

[0025] Another aspect of the present invention provides that sensitiveinformation, such as encryption keys, are stored in memory elements ofthe same integrated circuits that process the data using the keys. Thisconfiguration minimizes the transfer of the sensitive data throughdevice pins and along circuit board conductive paths that couldotherwise be monitored by sensing equipment.

[0026] Flip-chip manufacturing techniques described in the art are usedto enable attachment and connection of integrated circuit chips to eachother and to substrates. The present invention employs those techniquesto create a “chip sandwich” that protects the sensitive information,e.g., encryption keys (or data), from reverse engineering.

[0027] In one exemplary embodiment of the present invention, theintegrated circuit containing encryption keys is attached with itsactive side down to a substrate using solder bump flip-chip methodsdescribed by U.S. Pat. Nos. 4,670,770 issued to Tai, King L. and5,534,465 to Frye, R.C. et al of Bell Laboratories, or other techniquessuch as those described by C. W. Ho et al., “The Thin-Film Module as aHigh Performance Semiconductor Package,” IBM Journal of Research andDevelopment, Vol. 26, No. 3, May 1982, pp. 287-296, which discusses amulti-chip module of silicon chips attached to thin-film transmissionlines; or by P. Kraynak et al., “Wafer-Chip Assembly for Large ScaleIntegration,” IEEE Transactions on Electron Devices, Vol. ED-15, No. 9,Sep. 1968, pp. 660-663, where silicon chips are bonded “face down” on asilicon wafer. The above patents are hereby incorporated by reference,as if repeated herein in their entirety, including the drawings. Byflipping the chip over so that its active side is not exposed, thedesired physical protection described above is achieved.

[0028] If more protection is desired, circuitry may be added to theintegrated circuit that detects when the “chip sandwich” is pried apart.This detection circuitry may detect an interruption of power and/orground to the chip or a break in the continuity of one or moreconnections between the flip-chip and the substrate. When tampering isdetected, the circuitry deletes or corrupts the information in thememory elements using power from the system. Alternatively, one or morebatteries or other charge storage devices, such as a capacitors, can beused to provide power for the tampering detection circuitry and thescrambling or deletion circuitry. This configuration thereby providesthe electrical protection and isolation from probes describe above.

[0029] In another exemplary embodiment of one aspect of the presentinvention, a flip, chip is placed on top of a second integrated circuitchip that stores the keys, and the chip sandwich is packaged forassembly using conventional techniques. In addition, the flip-chipcontains a grid or pattern of electrically conductive lines thatmaintain continuity with the integrated circuit below. The integratedcircuit employs a circuit to determine whether continuity between thechips or along one or more of the conductive lines is interrupted orbroken (as might happen if the flip-chip were etched away to expose thememory elements below.) When an interruption or break in continuity isdetected, the stored key data is erased or scrambled.

[0030] In a third exemplary embodiment of one aspect of the presentinvention, the continuity detection circuitry and one or more chargestorage elements are placed on the flip-chip so that a standard off theshelf memory device may be used. This reduces the cost and complexity ofthe manufacturing process, thereby enabling use of this configuration inmore inexpensive applications.

[0031] A fourth exemplary embodiment of one aspect of the presentinvention employs a flip-chip mounted memory device, which is mounteddirectly onto an information processing device so that allinterconnections between the two devices (along which sensitive or keydata is transferred) lie within the “chip sandwich.”

[0032] For some memory devices, a high voltage is required to corrupt orerase the information contained therein. In these cases, the chargestorage device described in the above embodiments may include capacitorsthat are charged in parallel to a given voltage. When a continuity faultis detected, transistors switch the configuration from a parallelconfiguration to a series configuration, thereby producing a voltagesufficiently high to destroy or scramble the information stored in thememory elements.

[0033] Referring now to FIG. 1, which depicts an exemplary embodiment 10of an apparatus according to one aspect of the present invention in across-sectional view, a flip-chip 1 is mounted on an active chip 2.Grounds 3 and power supply leads 4 are shown coupled to the activedevice 2. Conventional packaging 6 surrounds the flip-chip 1 and activedevice 2 configuration. The active chip 2 and the flip chip 1 arecoupled by solder bonds 5. As discussed above, the continuity of theconnection between the flip-chip 1 and the active chip 2 is monitored.If continuity is broken, the memory is overwritten with random data orotherwise made unusable. Various techniques are possible, some of whichinclude writing random data, writing all ones or zeros, and applying anunsuitable voltage to the memory thereby destroying it.

[0034] Referring to FIG. 2, an alternative embodiment 20 of one aspectof the present invention is shown therein. In this embodiment 20, theflip-chip 21 is placed over an area on the active chip 22 in whichsensitive information, such as an encryption key, is stored. In thisembodiment 20, the flip-chip protects only the portion of the activechip 22 that contains the sensitive information. It is not necessary forthe flip chip 21 to cover the entire active chip 22. This exemplaryembodiment reduces the overall size of the device, for thoseapplications in which size is important, such as laptops, palm-baseddevices, etc.

[0035] Referring to FIG. 5, shown therein is a cross-sectional view ofan exemplary embodiment 50 of one aspect of the present invention.According to one aspect of the present invention, when encryption keymemory on the processing chip 51 or a dedicated memory chip (base chip)is used, a passive flip chip 52 makes continuity between flip-chip bondpads 53 and the base chip 51. As shown in FIG. 5, a sense circuit 54disposed on the active chip 51 senses when continuity is broken orotherwise interrupted and sends a signal to a read/write circuit 55 (seeFIG. 6) to write random data to memory 56. If the read/write circuit 55is not enabled, the sense circuit 54 can be triggered to trash thememory 56.

[0036] According to yet another aspect of the present invention, anapparatus for storing information includes two integrated circuits and adetection monitoring circuit. One integrated circuit has several chargestorage sites in which charges are stored representing the informationto be stored. Another integrated circuit is coupled to the otherintegrated circuit in a flip-chip configuration and prevents access tothe charge storage sites disposed therein. The detection circuit isdisposed in one of the integrated circuits and monitors a connectionbetween the two integrated circuits, and then alters the informationstored therein upon detecting a break in the connection. The detectioncircuit may also or alternatively detect a proximity of the twointegrated circuits. Depending upon the circuit layout of the circuitstoring the sensitive information, the other integrated circuit may bedisposed over only the portion of the integrated circuit storing thesensitive information. Configuring the two integrated circuits so thatthe one of the integrated circuits covers the conduction paths on theother storing the sensitive information (thereby making the conductionpaths inaccessible without separation of the two chips) is alsodesirable to prevent reverse engineering of the sensitive information.In addition, if the detection circuit monitors multiple conduction pathsbetween the two integrated circuits, the overall security of theconfiguration is enhanced.

[0037] Moreover, to further increase the security of the configuration,a read-write circuit is coupled to the detection circuit and the chargestorage sites. The detection circuit then enables the read-write circuitto write false data to the charge storage sites upon detection of abreak in continuity. False data can include any data that makes thestored information unusable, such as all ones, all zeros, random data,replacement but inaccurate data, etc.

[0038] In addition, an alternate power source is coupled to thedetection circuit, which provides power to the detection circuit uponremoval of normal supply power. The alternate power source also providespower to the read-write circuit upon removal of normal supply power.Furthermore, the alternate power source provides an unsuitable voltageto the charge storage sites upon detection of a break in the continuityby the detection circuit. An unsuitable voltage can include any voltagethat destroys the stored charges or otherwise corrupts the data storedtherein. The alternate power source can include one or more of thefollowing: a battery, a capacitor, and an energy storage device.Multiple capacitors in a parallel/series combination may be employed aswell. Configuring the capacitors in parallel for charging and in seriesfor discharging enables creating a high voltage, which may be necessaryin certain circumstances.

[0039]FIG. 6 depicts the exemplary embodiment shown in FIG. 5 in acircuit block diagram. The sense circuit 55 senses interruption in theconnection 58 between the flip chip 52 and the base chip 51. Uponsensing the interruption, the sense circuit 55 enables the read/writecircuit to write random data (or any other pattern, such as all ones)into the memory 56. If the read/write circuit is disabled or lackspower, the alternate power source 57 can re-enable the read/writecircuit 55. The alternate power source may consist of a capacitor, abattery, or other energy storage device. Alternatively, the sensecircuit may be included in the flip chip 52.

[0040]FIG. 7 depicts an exemplary embodiment in a flow chart form of acontinuity detection algorithm 70 according to one aspect of the presentinvention. The process 70 begins in a continuous loop checking thecontinuity of the flip-chip to the base chip (steps 71 and 72).Alternatively, the process can determine whether the proximity of theflip-chip to the base chip has been interrupted. There are numerouscircuits that may be used to detect continuity or proximity, which arewell known to one skilled in the art of circuit design. One suchimplementation applies a constant current through the interconnectionsbetween the flip-chip and the base-chip with a current detection circuiton the return side. If the flip-chip is pried apart from the base chipbreaking continuity, the current stops flowing, triggering the currentdetection circuit.

[0041] If continuity is broken (from step 72), the process 70 determinesthe status of the base chip. For example, the process 70 determineswhether the base chip is operating in the normal operating mode, orwhether power is on (step 73). If the base chip is in the normal state,and power is on, the process 70 causes the read/write circuit to writerandom data to the memory (step 76).

[0042] If the base chip is not in the normal state, e.g., normal poweris not being applied, then the process 70 determines whether thealternate power source can provide the necessary power to the read/writecircuit (step 75). If so, the process performs the random write (step76). If not, the process uses alternate power to damage the memory (77).

[0043] When the encryption key memory is on the flip-chip, prying offthe flip chip removes power from the flip-chip. Therefore, alternatepower must be used to destroy or erase memory data. A device to providethis power is fabricated on the flip-chip. Examples of alternate powersources include one or more of the following in combination or bythemselves: one or more capacitors, batteries, such as small integratedcircuit mounted batteries or tiny single use lithium batteries, etc.

[0044] According to one aspect of the present invention, a method forprotecting information contained within an integrated circuit, includessplitting the functionality of an integrated circuit into two separateintegrated circuits, and interconnecting the two separate integratedcircuits in an interlocking manner. In this embodiment, the two circuitscannot operate without being connected together. Moreover, theinterconnection can be monitored to further ensure the protection of thesensitive information stored therein. Furthermore, the informationcontained within the two separate integrated circuits can be destroyedupon detecting a break in the interconnection. As further protectionfrom reverse engineering of the information contained in the twocircuits, the two separate integrated circuits can be interconnected sothat all conduction paths and charge storage sites are not accessiblefrom the exterior, such as in a flip-chip configuration. In addition,rather than being destroyed, the information can be overwritten withrandom data upon detecting a break in the interconnection.

[0045]FIG. 8 depicts an exemplary embodiment 80 of an apparatus for usein an SRAM configuration according to one aspect of the presentinvention. Another potential solution to the problem being solved by thepresent invention involves separating the transistors 86, 87 of memorycells so that part of the transistors 86, 87 of the memory cell arefabricated on one chip 81 and the remainder are connected through solderbonds 89, 90 from the flip-chip 82. Such a device is depicted in FIG. 8.

[0046] In this embodiment 80, the input 85 and the output 86 areincluded on the same chip 81. Power Vdd 83 is received on the chip 81and the supply voltage Vss 88 is provided on the flip chip 82.Essentially, the functionality of a single chip is split into twoseparate chips so that each chip includes a portion of the totalfunctionality. Without the chips connected, the total functionality willbe lost. Consequently, one cannot determine the state of the memorycells when the chips are pried apart. Splitting the transistors 86, 87at the bonds 89, 90 will result in dissipation of the stored charge,thereby defeating any attempts at reverse engineering.

[0047] Hundreds of cells (even thousands, and perhaps millions) can befabricated below the bond pad (i.e., solder connection pad). Theconnections for the cells can be routed to the solder pad through viasin the passivation layer. When the flip chip is assembled, the memory iscomplete. If the flip-chip is removed, then the memory cell isnon-functional. In this embodiment, it is beneficial to have multiplefalse routings that will make reverse engineering of the circuitdifficult to impossible. Placing transistors below bond pads furtherincreases the difficulty of reverse engineering such a circuit.

[0048] Read-Only-Memory (ROM) presents a different set of problems. Onecan still separate the cells on the two chips. N-type cells can beplaced on one chip and P-type cells can be placed on another chip (i.e.,the flip chip) or vice versa. Alternatively, the N-type and P-typetransistors can be implemented on the same chip and the gates thatground the transistors can be placed on the flip-chip with connectionsgoing through the bond pads.

[0049] According to yet another aspect of the present invention, anapparatus for storing information in electronic form includes multiplememory cells and two integrated circuits. Each of the memory cellsincludes at least a first transistor pair and a second transistor pair.The memory cells stores the information in electronic form. The firstintegrated circuit has disposed therein each of the first transistorpairs of each of the memory cells. The second integrated circuit hasdisposed therein each of the second transistor pairs of each of thememory cells. The first and second integrated circuits are coupledtogether in a flip-chip configuration.

[0050] According to another aspect of the present invention, anapparatus for storing information in electronic form includes severalmemory cells and two integrated circuits. Each of the memory cellsincludes at least two transistors. The memory cells store theinformation in electronic form. One integrated circuit has disposedtherein both of the transistors forming the memory cells. The otherintegrated circuit has disposed therein a ground coupled to each of thetwo transistors in the one integrated circuit. As in the above, the twointegrated circuits are coupled together in a flip-chip configuration.Multiple solder bonds are provided via which the two transistors in eachmemory cell are coupled to the ground in the other integrated circuit.As discussed above, a continuity detection circuit monitors a continuityof connection between the two integrated circuits, and writes false datato the memory cells upon detecting a break in the continuity. Inaddition, two voltage supplies are provided both on the same chip, e.g.,the chip without the ground.

[0051]FIG. 9 depicts such an exemplary embodiment 91 of an apparatusaccording to one aspect of the present invention. In this embodiment 91,the transistors 94, 95 are coupled to ground 100 via the connectionsbetween the chips 92, 93. As a result, the memory cells will notfunction without connection to the flip chip 92. In this embodiment 91,the supply voltages Vdd and Vss are provided on the same chip 93. Input96 and output 97 are also provided on the same chip 93. Without theflip-chip, one would not know which cells are programmed. Thetransistors and gates can be arranged under the pads to further inhibitreverse engineering.

[0052]FIG. 10 depicts an exemplary embodiment of an apparatus accordingto one aspect of the present invention. In this embodiment 101 for usein an SRAM configuration, the transistors 102-105 are split so that thememory cell is split across two chips 106, 107. The transistors 102, 103are disposed in chip 106 and the other transistors 104, 105 are disposedin chip 107. Adjacent transistors are interconnected in a similarmanner.

[0053] In summary, the present invention provides several techniques anddevices for protecting sensitive information stored on an integratedcircuit. These techniques and devices prevent one from reverseengineering the circuit to decode the stored sensitive information bypreventing physical access to the stored sensitive information and byaltering the stored sensitive information upon detection of an attemptto defeat the physical security. In addition, the present inventionprovides a split integrated circuit whose functionality requires twoseparate chips to remain coupled together in a flip-chip manner.

[0054] While the present invention has been explained in terms ofseveral exemplary embodiments, the scope of the present invention is notlimited to the above exemplary embodiments but by the claims set forthbelow.

What is claimed is:
 1. A method for protecting information containedwithin an integrated circuit, comprising the steps of: splitting thefunctionality of a circuit into two separate portions; implementing thetwo separate portions as two separate integrated circuits;interconnecting the two separate integrated circuits in an interlockingmanner; and monitoring an interconnection of the two separate integratedcircuits.
 2. The method according to claim 1, further comprising thestep of destroying the information contained within the two separateintegrated circuits upon detecting a break in the interconnection of thetwo separate integrated circuits.
 3. The method according to claim 1,further comprising the step of interconnecting the two separateintegrated circuits so that all conduction paths and charge storagesites are not accessible from the exterior.
 4. The method according toclaim 1, wherein the two separate integrated circuits are connected in aflip-chip manner.
 5. The method according to claim 1, further comprisingthe step of writing random data to the memory upon detecting a break inthe interconnection of the two separate integrated circuits.
 6. Themethod according to claim 1, further comprising the step of disposing atleast a plurality of transistors storing sensitive information under aplurality of bond pads.
 7. The method according to claim 1, furthercomprising the step of disposing at least a plurality of gates storingsensitive information below a plurality of bond pads.
 8. An apparatusfor storing information comprising: a first integrated circuit having aplurality of charge storage sites in which charges are storedrepresenting the information to be stored; a second integrated circuitbeing coupled to the first integrated circuit in a flip-chipconfiguration and preventing access to the plurality of charge storagesites; a detection circuit being disposed in one of the first and secondintegrated circuits and monitoring a connection between the first andsecond integrated circuits, said detection circuit altering theinformation stored in the first integrated circuit upon detecting abreak in the connection between the first and second integratedcircuits.
 9. The apparatus according to claim 8, wherein the secondintegrated circuit is disposed over only a portion of the firstintegrated circuit.
 10. The apparatus according to claim 8, wherein thefirst integrated circuit includes a plurality of conduction paths, andsaid second integrated circuit is coupled to the first integratedcircuit so that the first integrated circuit covers the plurality ofconduction paths.
 11. The apparatus according to claim 8, furthercomprising a plurality of conduction paths coupling the first integratedcircuit to the second integrated circuit, wherein said detection circuitmonitors conduction continuity of one or more of the plurality ofconduction paths.
 12. The apparatus according to claim 8, furthercomprising a read-write circuit coupled to the detection circuit and theplurality of charge storage sites, said detection circuit enabling saidread-write circuit to write false data to the plurality of chargestorage sites upon detection of a break in continuity.
 13. The apparatusaccording to claim 8, further comprising an alternate power source beingcoupled to the detection circuit and providing power to the detectioncircuit upon removal of normal supply power.
 14. The apparatus accordingto claim 13, wherein the alternate power source also provides power tothe read-write circuit upon removal of normal supply power.
 15. Theapparatus according to claim 13, wherein the alternate power sourceprovides an unsuitable voltage to the plurality of charge storage sitesupon detection of a break in the continuity by the detection circuit.16. The apparatus according to claim 13, wherein the alternate powersource includes one or more selected from the group of: a battery, acapacitor, and an energy storage device.
 17. The apparatus according toclaim 13, wherein the alternate power source includes a plurality ofcapacitors coupled in a parallel configuration during charging, andswitched to a series configuration upon detection of a continuity fault.18. An apparatus for storing information comprising: a first integratedcircuit having a plurality of charge storage sites in which charges arestored representing the information to be stored; a second integratedcircuit being coupled to the first integrated circuit in a flip-chipconfiguration and preventing access to the plurality of charge storagesites; a proximity detection circuit being disposed in one of the firstand second integrated circuits and monitoring a proximity of the firstintegrated circuit relative to the second integrate circuit, saidproximity detection circuit altering the information stored in the firstintegrated circuit upon detecting a change in the proximity between thefirst and second integrated circuits.
 19. The apparatus according toclaim 18, wherein the second integrated circuit is disposed over only aportion of the first integrated circuit.
 20. The apparatus according toclaim 18, wherein the first integrated circuit includes a plurality ofconduction paths, and said second integrated circuit is coupled to thefirst integrated circuit so that the first integrated circuit covers theplurality of conduction paths.
 21. The apparatus according to claim 18,further comprising a read-write circuit coupled to the detection circuitand the plurality of charge storage sites, said proximity detectioncircuit enabling said read-write circuit to write false data to theplurality of charge storage sites upon detection of a change in theproximity between the first and second integrated circuits.
 22. Theapparatus according to claim 18, further comprising an alternate powersource being coupled to the detection circuit and providing power to thedetection circuit upon removal of normal supply power.
 23. The apparatusaccording to claim 22, wherein the alternate power source also providespower to the read-write circuit upon removal of normal supply power. 24.The apparatus according to claim 22, wherein the alternate power sourceprovides an unsuitable voltage to the plurality of charge storage sitesupon detection of a change in the proximity between the first and secondintegrated circuits.
 25. The apparatus according to claim 22, whereinthe alternate power source includes one or more selected from the groupof: a battery, a capacitor, and an energy storage device.
 26. Anapparatus for storing information in electronic form comprising: aplurality of memory cells, each of which plurality of memory cellsincludes at least a first transistor and a second transistor, saidplurality of memory cells storing the information in electronic form, afirst integrated circuit on which is disposed each of the firsttransistors of each of the plurality of memory cells; and a secondintegrated circuit on which is disposed each of the second transistorsof each of the plurality of memory cells, wherein said first and secondintegrated circuits are coupled together in a flip-chip configuration.27. The apparatus according to claim 26, further comprising a pluralityof solder bonds via which the first and second transistors in eachmemory cell are coupled together.
 28. The apparatus according to claim27, further comprising a continuity detection circuit monitoring acontinuity of connection between the first and second integratedcircuits, and writing false data to the plurality of memory cells upondetecting a break in the continuity.
 29. The apparatus according toclaim 26, further comprising a first voltage supply and a second voltagesupply, wherein said first voltage supply is disposed on the firstintegrated circuit and the second voltage supply is disposed on thesecond integrated circuit.
 30. An apparatus for storing information inelectronic form comprising: a plurality of memory cells, each of whichplurality of memory cells includes at least a first transistor pair anda second transistor pair, said plurality of memory cells storing theinformation in electronic form, a first integrated circuit on which isdisposed each of the first transistor pairs of each of the plurality ofmemory cells; and a second integrated circuit on which is disposed eachof the second transistor pairs of each of the plurality of memory cells,wherein said first and second integrated circuits are coupled togetherin a flip-chip configuration.
 31. The apparatus according to claim 30,further comprising a plurality of solder bonds via which the first andsecond transistor pairs in each memory cell are coupled together. 32.The apparatus according to claim 30, further comprising a continuitydetection circuit monitoring a continuity of connection between thefirst and second integrated circuits, and writing false data to theplurality of memory cells upon detecting a break in the continuity. 33.The apparatus according to claim 30, further comprising a first voltagesupply and a second voltage supply, wherein said first voltage supply isdisposed on the first integrated circuit and the second voltage supplyis disposed on the second integrated circuit.
 34. An apparatus forstoring information in electronic form comprising: a plurality of memorycells, each of which plurality of memory cells includes at least a firsttransistor and a second transistor, said plurality of memory cellsstoring the information in electronic form, a first integrated circuiton which is disposed each of the first and second transistors of each ofthe plurality of memory cells; and a second integrated circuit on whichis disposed a ground coupled to each of the first and secondtransistors, wherein the first and second transistors are coupled to theground via the second integrated circuit, and the first and secondintegrated circuits are coupled together in a flip-chip configuration.35. The apparatus according to claim 34, further comprising a pluralityof solder bonds via which the first and second transistors in eachmemory cell are coupled to the ground in the second integrated circuit.36. The apparatus according to claim 34, further comprising a continuitydetection circuit monitoring a continuity of connection between thefirst and second integrated circuits, and writing false data to theplurality of memory cells upon detecting a break in the continuity. 37.The apparatus according to claim 34, further comprising a first voltagesupply and a second voltage supply, wherein said first and secondvoltage supplies are disposed on the first integrated circuit.